The present invention relates generally to semiconductor manufacturing processes, and more particularly to methods and structures for monitoring such processes.
Semiconductor circuit devices are typically manufactured by a sequence of steps, each of which can deposit and/or modify a layer formed in or on a wafer. While it would be ideal for each step of a process to be absolutely repeatable, in most cases, manufacturing steps can vary over time. Consequently, it may be desirable to monitor particular steps. Thus, if a particular step begins to vary, the process step can be adjusted to provide the desired result.
One common form of process monitoring is to provide monitoring wafers. A monitoring wafer may be run through a set of predetermined manufacturing steps and subsequently examined to determine how one or more of the steps are performing. Because data provided from a monitoring wafer could be used to adjust one or more process steps, it follows that the more reliable and/or accurate a monitoring wafer is, the better a process step can be adjusted.
Spacings, such as trenches or the like, can be an important feature to monitor. As but one example, substrate trenches formed in shallow trench isolation process steps may affect various device features. However, because such substrate trenches can be subject to uncontrollable variation, it can be difficult to monitor particular features that may vary with substrate trench depth.
As another example, silicon-on-insulator (SOI) processes can include spacings (trenches) that separate one semiconductor island (mesa) from another. During SOI process development it can be desirable to characterize how a particular feature can be formed on, and with respect to, such islands. However, an SOI development process monitoring step is typically destructive, in that a wafer may have to be destroyed. Thus, it may be very expensive to develop/monitor/characterize physical features in a SOI process, as many SOI wafers may have to be destroyed.
To better understand the present invention, a first conventional process monitoring method and structure will now be described.
A method of forming a structure that may be used to monitor a process step is shown in FIGS. 5A to 5D. FIGS. 5A to 5D show a series of cross sectional views of a shallow trench isolation (STI) formation process. In the conventional example, a chemical-mechanical polishing (CMP) step can be monitored by measuring a step height of a material that is removed by the CUT step. More particularly, a step height of an insulating material deposited in a substrate trench is measured.
FIG. 5A shows a semiconductor device 500 that may include a substrate 502 on which a trench etch mask 504 may be formed. A trench etch mask 504 can selectively expose portions of a substrate 502 where a trench is to be formed. A substrate 502 may be formed from monocrystalline silicon. A trench etch mask 504 may be formed from a layer of deposited silicon nitride that is patterned with conventional photolithographic techniques. A thin layer of silicon dioxide 505 may be formed over a substrate 502.
FIG. 5B shows trenches 506 that may be formed in a substrate 502 by etching with a trench etch mask 504. Each trench 506 may have a trench depth, one of which is shown by measurement 508. It is noted that a trench etching step may be subject to some variation. Consequently, a trench depth (such as 508) may vary across a wafer and/or between different lots. This will be discussed in more detail below. A trench 508 may be formed by an anisotropic plasma etch, as but one example.
FIG. 5C shows a trench insulating material 510 that has been formed in trenches 506. Such a trench insulating material 510 can provide substrate isolation for particular circuit devices formed in a substrate 502. A trench insulating material 510 may include silicon dioxide deposited with a high density plasma (HDP). As shown in FIG. 5C, following the deposition of a trench insulating material 510, a resulting top surface of a semiconductor device can be uneven. It may therefore be desirable to planarize such a surface.
FIG. 5D shows semiconductor device 500 following a planarizing step. A planarizing step may include chemical mechanical polishing. A resulting structure such as that shown in FIG. 5D may then be used to monitor the planarization process. In particular, a trench insulator step height, shown as 512 and residual nitride thickness may be measured. Such a measurement, ideally, could give an indication as to the rate and/or amount of trench insulating material being removed by a planarization step, or the like.
Thus, a monitoring wafer could be removed at this point, and a trench insulator step height 512 and residual nitride thickness could be measured by taking a cross sectional view of the wafer, or the like.
It has been found that a resulting trench insulator step height can vary according to trench depth. Unfortunately, as noted above, trench depth may vary across a wafer and/or across a lot. Consequently, a given monitoring wafer (or wafer portion) may provide different measurements for a trench insulator step height depending upon a depth of the corresponding trench.
One conventional way of attempting to compensate for such variation is illustrated in FIGS. 6A and 6B. FIGS. 6A and 6B are graphs showing experimentally determined relationships between trench depth and resulting trench insulator step height. In particular, FIG. 6A shows a relationship between trench depth, trench insulator step height, and wafer position. FIG. 6B shows a relationship between trench depth and trench insulator step height. In both of the graphs, as trench depth decreases, step height increases. FIGS. 7A and 7B provide various examples of such relationships in side cross sectional views. FIG. 7A shows the range of values in FIG. 6A. FIG. 7B shows the range of values in FIG. 6B.
FIGS. 7A and 7B include many of the same structures shown in FIGS. 5A to 5D. To that extent like structures will be referred to by the same reference character. FIG. 7A shows a maximum trench depth and corresponding minimum step height 512 and a minimum trench depth and corresponding maximum step height 512xe2x80x2 for the values shown in FIG. 6A. Similarly, FIG. 7A shows a maximum trench depth and corresponding minimum step height 512 and a minimum trench depth and corresponding maximum step height 512xe2x80x2 for the values shown in FIG. 6B. As shown in FIG. 6B, a minimum step height 512 can be a negative value.
A drawback to the above conventional approach is that a monitoring measurement may not be a direct measurement, but rather an indirect measurement. That is, simply measuring a trench insulator step height does not necessarily give an accurate indication of how a CMP step is performing, as the corresponding trench depth must also be measured. The two values may then be applied to an experimentally determined relationship, such as those shown in FIGS. 7A and 7B.
Still further, it is not clear that experimental results may accurately represent a CMP step for all cases. As but a few examples, if a trench width or trench insulator material is changed, a new experiment may have to be run to determine a relationship between trench depth and trench insulator step height.
In light of the above described background art and example, it would be desirable to arrive at an improved way of monitoring a manufacturing step, where the monitoring includes measuring a feature that may vary according to trench depth.
Having described a first conventional process monitoring method and structure, a second conventional example will now be described.
FIG. 8 shows a conventional SOI monitoring structure. A SOI monitoring structure 800 may include a portion of a SOI wafer having desired features formed thereon. Because a monitoring structure 800 is formed on an SOI wafer, a monitoring structure may include a substrate 802, a substrate insulator 804, and a number of silicon islands 806 formed on a substrate insulator 804.
As is well known, an SOI device may include various features formed in and/or with islands 806. In the particular example of FIG. 8, such features may include a transistor having a source region 808, a channel region 810, a drain region 812, a gate dielectric 814, a gate 816, surrounding gate sidewalls 818, and a gate top insulator 820. In addition, contacts 822 may be formed to an island 806. Such features, and others not mentioned here, can be monitored by viewing a conventional monitoring structure 800 in cross section.
A drawback to such a conventional approach is that in order to monitor various SOI features an SOI wafer must typically be destroyed. Because SOI wafers are expensive, this can add expense to a manufacturing/development operation.
In light of the above described background art and example, it would be desirable to arrive at an improved way of monitoring a SOI process that can be more cost-effective than conventional approaches.
According to one embodiment, a process monitoring structure may include monitoring trenches that are formed through a substrate emulation layer and terminate at an etch stop layer. Such monitoring trenches can have a trench depth equal to a thickness of a substrate emulation layer. Such a structure may provide trenches having a depth that can be subject to less variation than trenches that are formed in a substrate. Further, such a structure may be used to monitor a semiconductor-on-insulator (SOI) structure, without having to sacrifice a SOI wafer.
According to one aspect of the above embodiment, a substrate emulation layer may include polysilicon and an etch stop layer may include silicon dioxide.
According to another embodiment, a method of forming a process monitoring structure may include forming an etch stop layer on a substrate. A trench emulation layer may then be formed over an etch stop layer. Monitor trenches can be formed by etching through a trench emulation layer to an etch stop layer, which can make a uniform trench depth. This is in contrast to conventional approaches, which may include step height variation from a shallow trench isolation step.
According to one aspect of the above embodiment, monitor trenches may be formed by etching with a shallow trench isolation (STI) etch mask.
According to another aspect of the above embodiment, a shallow trench insulator may be formed over monitor trenches and then planarized. A resulting trench insulator step height may be measured to monitor a planarization process. Results obtained from monitor trenches may be more accurate than those obtained from substrate trenches, which can be subject to greater variation than monitor trenches.
According to another aspect of the above embodiment, SOI structures may be formed with monitor trenches. Such SOI structures may then be examined to monitor/develop/characterize one or more SOI physical process steps. Such structure may thus be formed on a less expensive wafer than a SOI wafer.
According to another embodiment, a method of monitoring a process step may include forming a monitoring structure that includes monitor trenches formed in a first layer. A monitor structure may then run through one or more process steps that form a feature. A corresponding feature formed on, e.g., a production wafer may typically be formed in, with, and/or in relation to trenches formed in a different layer. Because, a monitor trench may be subject to less variation than trenches formed in a different layer, resulting features formed in, with, and/or in relation to a monitor trench may provide a better indication of how process steps are performing. Further, a monitoring structure may be formed to monitor one or more SOI features, but can be formed on a non-SOI wafer. Thus, a more expensive SOI wafer does not necessarily have to be sacrificed.
According to one aspect of the above embodiment, a monitor structure may be configured to monitor a chemical-mechanical polishing step for a shallow trench isolation insulator.
According to another aspect of the above embodiment, a monitor structure may be configured to monitor SOI physical features formed on a non-SOI wafer.